Semiconductor device with current confinement structure

ABSTRACT

The present invention relates to a semiconductor device ( 1 ) with one or more current confinement regions ( 20,45 ) and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device ( 1 ) comprises an active layer ( 10 ), a current conduction region ( 4 ), one or more current confinement regions ( 20,45 ) adjacent the current conduction region. The current conduction region ( 4 ) and current confinement region ( 20,45 ) are arranged to channel an applied electric current to the active layer ( 10 ). The or each current confinement region includes both a metal-doped current blocking structure ( 45 ) and a p-n junction current blocking structure ( 20 ). The p-n current blocking structure ( 20 ) is between the current conduction region ( 4 ) and the metal-doped current blocking structure ( 45 ).

[0001] The present invention relates to a semiconductor device with oneor more current confinement regions and to a method of manufacturingsuch a device, particularly buried heterostructure light emittingdevices such as semiconductor lasers and light emitting diodes.

[0002] Buried heterostructure light emitting devices commonly havecurrent confinement regions defined by areas of high resistivity thatchannel current to an optically active layer within the structure. Indevices using InGaAsP/InP materials, current confinement regions havebeen employed based on a reverse-biased p-n or n-p diode structure. Suchstructures provide high resistivity, and low leakage currents, and arewidely used in fibre optic communication systems across a range ofoperating frequencies. At operating frequencies about 1 GHz, however,the performance of such devices becomes limited by the capacitance ofthe current blocking structure, owing to the charge on the reversebiased diode junction.

[0003] Other current blocking structures have therefore been developed,for example Fe-doped InP-based layers, as described in U.S. Pat. No.4,660,208. Such Fe-doped layers have a lower capacitance than structuresbased on a reverse biased junction, but do not have as high aresistivity. This lower resistivity also limits operation and devicelifetime at high frequencies, because of the resulting higher deviceoperating temperatures. In order to avoid excessive temperatures, itbecomes necessary to use a lower drive voltage, and this in turn limitsthe achievable bandwidth of a device based on Fe-doped material.

[0004] In recent years there has been an increasing demand for fibreoptic communication links having a bandwidth in excess of 1 GHz, forexample up to 10 GHz. It is an object of the present invention toprovide a semiconductor device that addresses these issues.

[0005] Accordingly, the invention provides a semiconductor devicecomprising an active layer, a current conduction region, one or morecurrent confinement regions adjacent the current conduction region, thecurrent conduction region and current confinement region being arrangedto channel electric current to the active layer, wherein the or eachcurrent confinement region includes both a metal-doped current blockingstructure and a p-n junction current blocking structure, the p-n currentblocking structure being between the current conduction region and themetal-doped current blocking structure.

[0006] It has been found that the p-n current blocking structure nearestthe current conduction region then provides high resistivity and goodhigh frequency performance at high temperatures, while the reduction inthe volume of the p-n current blocking structure and use of themetal-doped second current blocking structure further away from thecurrent conduction region provides reduced parasitic capacitance.

[0007] In some type of device, for example buried heterostructure laserdiodes, the device includes a substrate, a mesa stripe on the substrateand an active layer in the mesa stripe. The current conduction regionthen channels current through the active layer.

[0008] The mesa stripe may have one or more side walls that rise abovethe substrate. The active layer then extends to the side wall(s) and theactive layer is covered at the side walls by the p-n blocking structure.

[0009] In preferred embodiments of the invention, the mesa side wallsslope laterally away from the active layer towards the metal-dopedcurrent confinement structure. Also in a preferred embodiment, themetal-doped current confinement structure abuts the p-n currentconfinement structure along a substantially vertical interface.

[0010] Also according to the invention, there is provided a method offorming semiconductor device comprising an active layer, a currentconduction region, one or more current confinement regions adjacent thecurrent conduction region, the current conduction region and currentconfinement region being arranged to channel electric current to theactive layer, wherein the method comprises the steps of:

[0011] i) growing upon a semiconductor substrate a plurality ofsemiconductor layers, including the active layer and the currentconduction region by which electric current may be applied to the activelayer;

[0012] ii) growing adjacent the active layer a p-n junction currentblocking structure; and

[0013] iii) growing adjacent the p-n junction current blocking structurea metal-doped current blocking structure, the p-n-junction currentblocking structure and the metal-doped current blocking structuretogether forming a current confinement region for channelling electriccurrent to the current conduction region.

[0014] In one embodiment of the invention, prior to step ii), a firstetch mask is formed over the active layer, said first etch mask definingduring an etching process an area of the active layer adjacent thecurrent conduction region to be removed by the etching. Then, prior tostep iii) a second etch mask is formed over the active layer and the p-njunction current blocking structure adjacent the current conductionregion, said second etch mask defining during an etching process an areaof p-n junction current blocking structure not adjacent the active layerto be removed by the etching.

[0015] This second etch mask may then remain in place during the growthof the metal-doped current blocking structure in step iii).

[0016] In order to achieve a sufficiently uniform width of the firstcurrent blocking structure, the second etch mask is then alignedlaterally with the first etch mask, typically to an accuracy of about10% to 20% of the width of the second etch mask. In one preferredembodiment of the invention, the second etch mask is laterally widerthan the first etch mask.

[0017] In another embodiment of the invention, prior to step ii), anetch mask is formed over the active layer, said etch mask definingduring a first etching process an area of the active layer adjacent thecurrent conduction region to be removed by the etching. The etch maskremains during the growth of the p-n current blocking structure in stepii). Finally, the etch mask defines during a second etching process anarea of the p-n junction current blocking structure not adjacent theactive layer to be removed by the etching.

[0018] This etch mask may then remain in place during the growth of themetal-doped current blocking structure in step iii).

[0019] Because this process uses only one mask for the formation of thefirst current conduction structure and the second current conductionstructure, the process is self-aligning for these two current blockingstructures.

[0020] The invention will now be described by way of example, withreference to the accompanying drawings, in which:

[0021]FIG. 1 is a schematic cross-section of a buried heterostructuresemiconductor laser device according to a first embodiment of theinvention, comprising an active layer within a buried mesa stripe, acurrent conduction region for channelling current to the active layer,and current confinement regions consisting of two distinct currentconfinement structures on each side of the heterostructure;

[0022] FIGS. 2 to 4 show process steps for creating a first currentconfinement structure adjacent the mesa stripe, formed from a p-njunction current blocking layer;

[0023]FIGS. 5 and 6 show process steps for creating a second currentconfinement structure adjacent the first current blocking layer, formedfrom a metal-doped current blocking layer;

[0024]FIG. 7 shows the formation of cladding, cap, and electricalcontact layers leading to the device of FIG. 1;

[0025] FIGS. 8 to 10 show process steps for a second embodiment of theinvention;

[0026]FIGS. 11 and 12 show plots of small signal response againstoperating frequency at respectively 25° C. and 85° C. for the laserdevice of FIG. 1; and

[0027]FIG. 13 shows a plot of fall time against small signal responsefor the laser device of FIG. 1, and for a various types of knownsemiconductor laser device.

[0028]FIG. 1 shows, not to scale, a cross-section of a semiconductordevice 1 according to the invention, here a buried heterostructure laserdiode suitable for use as a transmitter in a high speed fibre-optic linkoperating at 1.55 μm. Currently, high speed links operate at 2.5 or 10Gbits/s, and bit rates of up to 40 Gbits/s have been demonstrated in thelaboratory.

[0029] Referring now also to FIG. 2, the device 1 is formed startingfrom a wafer 3 that is 32 mm square, and that has an n⁻⁻-InP substrate 2doped to around 10¹⁹/cc, on which is grown a 2 μm thick n⁻-InP bufferlayer 8 doped to around 10¹⁸/cc. An active layer 10 is grown on thebuffer layer 8 according to known techniques for fabricating planaractive lasers for a laser diode—the active layer could be a bulk regionor a strained multiple quantum well (SMQW) structure. An example of anSMQW device is discussed in W. S. Ring et al, Optical Fibre Conference,Vol. 2, 1996 Technical Digest Series, Optical Society of America. Thetype of active layer employed is not critical to the invention.

[0030] In the present example, the laser diode 1 has a quaternaryIn_(x)Ga_(1−x)As_(1−y)P_(y) active layer 10 that may be between about100 nm to 300 nm thick. The active layer 10 is topped by another bufferlayer 12, also called a P₀-layer, formed from p⁺-InP, grown to bebetween about 400 nm to 1 μm thick.

[0031] Although not illustrated a DFB grating for the laser diode 1 canbe contained in the n⁻-InP buffer layer 8 or in an additional p-InGaAsPgrating layer.

[0032] Then, using well-known fabrication technology, the wafer 3 iscoated with an oxide layer 16 as shown in FIG. 2. The oxide layer may beSiO₂ deposited by a plasma enhanced chemical vapour deposition (PECVD)process. It should, however, be noted that silicon nitride would be asuitable alternative choice to SiO₂. As shown in FIG. 3, the oxide layer16 is photolithographicly patterned with a photoresist to leave apatterned mask 26, and etched to remove in areas not covered by thepatterned mask the P₀-layer 12, the active layer 10, and all but 200 nmof the buffer layer 8. In this example layers 8, 10 and 12 are removedin a wet-etch process that undercuts the patterned mask 26 by about 200nm to 500 nm.

[0033] The layers 8, 10, and 12 are removed in all areas except along amesa stripe 14 structure that extends perpendicular to the plane of thedrawing, and which rises above the level of the substrate 2. The mesastripe 14 has left and right opposite side walls 21,22 that togetherwith the buffer layer 8 and the P₀-layer 12 form a current conductionregion 4 for an applied current I, and have the effect of guiding anoptical mode 15 along the active layer 10 within the stripe 14.

[0034] The width of the mesa stripe 14 varies depending on theparticular device, but for opto-electronic devices such as laser diodes,the ridge stripe 14 is usually between 1 μm and 10 μm wide. The ridgestrip 14 rises 1 μm to 2 μm above the surrounding substrate 2.

[0035] A first current blocking structure 20 is then grown on the etcheddevice up to approximately the level of the patterned mask 26, firstwith a p-doped InP layer 17, and then with an n-doped InP layer 18. Thethicknesses of the p-doped and n-doped layers are similar. These InPlayers 17,18 form a p-n junction that is insulating when the laser diode1 is forward biased.

[0036] After deposition of the first current blocking structure 20, thePECVD oxide layer 16 is removed with 10:1 buffered HF from the ridgestrip 14 to expose again the P₀-layer 12. This leaves an etched andcoated wafer 23 comprising the substrate 2, the mesa stripe 14 and thefirst current blocking structure 20 abutting the opposite sides 21,22 ofthe mesa stripe 14.

[0037] The etched and coated wafer 23 is coated with an oxide layer,such as an SiO₂ layer or silicon nitride layer deposited by PECVD, whichis then pholithographicly patterned and etched as described above toleave a second patterned mask 36. The second patterned mask 36 isaligned along the length of the mesa stripe 14, but is wider than themesa stripe, so that the mask 36 and extends at least 1 μm andpreferably 2 μm laterally beyond the junction between each mesa side21,22 and a top surface 37 of the P₀-layer 12.

[0038] The P₀-layer 12, the active layer 10, and preferably all of thebuffer layer 8 are then removed in a reactive ion plasma dry etchprocess, which cuts substantially vertical sides walls 41,42 throughthese layers. The resulting etched structure 44 is shown in FIG. 5.

[0039] A second current blocking structure 45 is then grown using aMOVCD process on the exposed semiconductor surfaces of the etchedstructure 44. This current blocking structure is formed from a Fe-dopedInP-based layer 46 topped by an n⁻-InP layer 47. Alternatively, insteadof iron, the metal dopant could be ruthenium or chromium. The thicknessof the Fe—InP layer is about 1 μm to 2 μm, so that this extends almostup to the mask 36. The n⁻-InP layer is about 200 nm to 500 nm thick, andextends just above the mask 36. The second current blocking structure 45therefore abuts the side walls 41,42 of the first current blockingstructure 20 along a substantially vertical interface, and the firstcurrent blocking structure 20 abuts the side walls 21,22 of the mesastripe 14. Because the second current blocking structure 45 extendsdeeper within the current blocking region than the first currentblocking structure 20, the second current blocking structure 45 alsoabuts a portion of the n⁻-InP buffer layer 8 along a substantiallyvertical interface.

[0040] The n⁻-InP layer 47 in the second blocking structure 45 blocksthe conduction of holes through the blocking structure as well as actingas a barrier to the diffusion of Zn into the metal-doped layer 46.

[0041] After the growth of the second current confinement structure 45,the patterned oxide layer 36 is removed with 10:1 buffered HF from theridge strip 14 to expose again the P₀-layer 12.

[0042] A cladding layer 48 formed from p⁺-InP is then grown above theP₀-layer 12 and current blocking structures 20,45 to a thickness ofabout 2 μm to 3 μm. The final semiconductor layer is a 100 nm to 200 nmthick ternary cap layer 49 deposited on the cladding layer 48. The caplayer 49 is formed from p⁺⁺-GaInAs, highly doped to around 10¹⁹/cc, inorder to provide a good low resistance ohmic contact for electricalconnection to the current conduction region 4 of the mesa stripe 14. Asan alternative to a ternary cap layer, it is possible to use aquaternary InGaAsP cap layer.

[0043] Metal 50 is then vacuum deposited on the cap layer 49 using wellknown techniques in two stages, first with a TiPt layer that ispatterned using a lift-off process, and then final depositing of a TiAulayer, followed by metal wet etch in a photolithographically definedareas. The remaining TiAu layer forms a contact pad 52 with good ohmiccontact through the cap layer 49.

[0044] The resulting wafer 54 is then thinned to a thickness of about 70μm to 100 μm in a standard way, in order to assist with cleaving. Thethinned wafer is then inscribed and cleaved in a conventional processfirst transversely into bars about 350 μm wide, and then each bar iscleaved into individual devices 200 μm wide. The cleaved device 1 isabout 350 μm long (i.e. in the direction of the mesa 14) and about 200μm wide.

[0045] A Ti/Au metal layer 53 is then deposited by sputtering on therear surface of the wafer, so enabling the device to be soldered onto aheat sink.

[0046] Although not shown, after testing the device 1 may F be packagedin an industry standard package, with a single mode optical fibrecoupled with a spherical lens to an output facet of the laser diode, andwith gold bond wires soldered onto the metalised contact 52.

[0047] The InGaAs/InP device 1 described above therefore incorporates acompound current confinement region formed from a reverse-biased p-nstructure nearest the active region 10, and further away from the activeregion 10, a metal-doped InP-based layer. The p-n structure nearest theactive region provides superior temperature performance, compared with apurely metal-doped current confinement region, while at the same timeexcess leakage current through the first current confinement structureat high operating frequencies due to parasitic capacitance from thereverse-biased diode structure is reduced owing to the reduced volume oramount of such a structure. Therefore, as will be described in furtherdetail below, the invention provides a high resistivity currentconfinement region, and low leakage currents, across a wide range ofoperating temperatures. The invention also permits the use of higherdrive voltages, which are useful in achieving high-speed operation.

[0048] FIGS. 8 to 10 show how the process described above may bemodified, in a second embodiment 101 of the invention, where featurescorresponding with those of FIGS. 1 to 7 are given similar referencenumerals incremented by 100. The process used to create the secondembodiment 101 differs from that used to create the first embodiment 1in that only one patterned inorganic mask 126 need be deposited on thewafer. This mask is used in the modified process in such a way that themask 126 assures the self-alignment of the first current blockingstructure 120 with respect to the second current blocking structure 145.

[0049] Here, the mask 126 is wider than the corresponding patterned maskshown in FIG. 3. However, the layers of the first current blockingstructure 120, the p-doped InP layer 117 and n-doped InP layer 118, canstill be grown up approximately to the level of the mask 126. The mask126 is wide enough so that width of the first current blocking layerbeneath the mask is sufficient for good high-frequency performance, asdescribed above. Therefore, the first current blocking structure 120 andunderlying buffer layer 8 outside the area of the mask 126 can beremoved in a reactive ion plasma etching process, as shown in FIG. 9.

[0050] The wafer is then processed in a similar manner to the firstembodiment. The second current blocking structure 145 is formed with a 1μm to 2 μm thick Fe-doped InP layer 146, overlain with a 200 nm to 500nm thick n⁻-InP layer up to about the level of the top of the mesa strip114. The mask 126 is then removed, followed by formation of the claddinglayer 148, cap layer 149, metallic contact layer 150, and formation of acontacts 152,53 above the mesa stripe 114 and the substrate 2.

[0051] The performance of a semiconductor laser diode according to theinvention is shown in FIGS. 11 to 13. The small signal response againstoperating frequency at respectively 25° C. and 85° C. is shownrespectively in FIGS. 11 and 12, as a plot of the small signal initialslope S21 in dBo (dB optical) against operating frequency in GHz. Thesmall signal drop off crosses −3 dB near 15 GHz. The signal fall time(90% to 10%) was measured to be about 85 ps. This is much better thanthe signal fall time of a standard buried heterostructure laser diodedevice with only a p-n junction current blocking layer either side ofthe mesa stripe, which is typically between 120 ps to 250 ps.

[0052] In order to test the efficiency of the laser diodes , dcmeasurements of the slope of the light output vs drive current were madeat 25° C. and at 85° C. The slopes at typical drive currents of 8.5 mA(at 25° C.) and 29 mA (at 85° C.) were measured and then divided by theslopes at about 1 mA. The ratio of these slopes is a measure of thedevice's efficiency, which was determined to be 0.86 at 25° C. and 0.71at 85°. For devices of this sort, efficiency figures such as this areconsidered to be very good.

[0053]FIG. 13 shows a plot of fall time for the laser device of FIG. 1,within the circle labelled with reference numeral 70, compared against arange of other types of semiconductor laser devices. As can be seen, thetypical fall time and S21 initial slope characteristics are very good.

[0054] Semiconductor devices according to the invention provide a highoperating bandwidth and good lifetime characteristics. The process stepsinvolved may be similar to other standard steps used in the fabricationof such devices. There is no need for additional expensive processingequipment. The tolerances in the alignment of the mask or masks used toform the two current confinement structures are not unduly difficult toachieve using standard processing equipment.

[0055] Although the present invention has been described specificallyfor the example of a laser diode, the invention is applicable to anyhigh speed semiconductor device where current blocking regions help tochannel current through a current conduction region, for example ridgewaveguide type lasers, pump lasers, edge emitting light emitting diodes,edge photodetectors, surface emitting laser and light emitting diodes,and top-entry photodetectors. Another example is an optical waveguidewith a split into two waveguides at a Y-junction. This may haveelectrically driven or modulated active optical regions in two or threeof the arms of the “Y”, for example an optical amplifier or modulator.It may then be desirable to provide a current blocking region at thejunction of the three arms, where there may be three separate conductionregions.

[0056] The invention described above have been described for a devicebased on an n⁻⁻-InP substrate, and having a first current blockingstructure formed from a reverse biased p-n junction in laterallyadjacent contact with the active layer structure, and a second currentblocking structure formed from a metal-doped/n⁻ InP layer structure inlaterally adjacent contact with the first current blocking structure.However, it is to be appreciated that the invention can also be appliedto other types of devices, for example those based on a p⁺⁺-InPsubstrate. In this case, the first current blocking structure may be areverse biased n-p junction, and the second current blocking structuremay include a metal-doped/p⁺ InP layer structure in laterally adjacentcontact with the first current blocking structure. The term “p-njunction current blocking structure” therefore includes such a reversebiased n-p junction.

1. A semiconductor device (1,101) comprising an active layer (10), acurrent conduction region (4;104), one or more current confinementregions (20,45;120,145) adjacent the current conduction region, thecurrent conduction region (4;104) and current confinement region(20,45;120,145) being arranged to channel electric current to the activelayer (10), wherein the or each current confinement region includes botha metal-doped current blocking structure (45;145) and a p-n junctioncurrent blocking structure (20;120), the p-n current blocking structure(20;120) being between the current conduction region (4;104) and themetal-doped current blocking structure (45;145).
 2. A semiconductordevice as claimed in claim 1, the device including a substrate (2), amesa stripe (14;114) on the substrate (2) and an active layer (10) inthe mesa stripe (14;114), in which the current conduction region (4;104)channels current through the active layer (10).
 3. A semiconductordevice as claimed in claim 2, in which the mesa stripe (14;114) has oneor more side walls (21,22;121,122) that rise above the substrate (2),the active layer (10) extending to the side wall(s) (21,22;121,122) andthe active layer (10) being covered at the side walls (21,22;121,122) bythe p-n blocking structure (20;120).
 4. A semiconductor device (1) asclaimed in claim 2 or claim 3, in which the mesa side walls(21,22;121,122) slope laterally away from the active layer (10) towardsthe metal-doped current confinement structure (45;145).
 5. Asemiconductor device (1) as claimed in any preceding claim, in which themetal-doped current confinement structure (45;145) abuts the p-n currentconfinement structure (20;120) along a substantially vertical interface(41,42;141,142).
 6. A semiconductor device (1) as claimed in anyprevious claim, in which the device (1) is a buried heterostructurelaser diode device.
 7. A semiconductor device (1) as claimed in anypreceding claim, in which the device (1) is formed from III-Vsemiconductor materials.
 8. A method of forming semiconductor device(1,101) comprising an active layer (10), a current conduction region(4;104), one or more current confinement regions (20,45;120,145)adjacent the current conduction region, the current conduction region(4;104) and current confinement region (20,45;120,145) being arranged tochannel electric current to the active layer (10), wherein the methodcomprises the steps of: i) growing upon a semiconductor substrate (2) aplurality of semiconductor layers, including the active layer (10) andthe current conduction region (4;104) by which electric current may beapplied to the active layer (10); ii) growing adjacent the active layer(10) a p-n junction current blocking structure (20;120); and iii)growing adjacent the p-n junction current blocking structure (20;120) ametal-doped current blocking structure (45;145), the p-n-junctioncurrent blocking structure and the metal-doped current blockingstructure (45;145) together forming a current confinement region forchannelling electric current to the current conduction region (4;104).9. A method as claimed in claim 8, in which: prior to step ii) a firstetch mask (26) is formed over the active layer (10), said first etchmask (26) defining during an etching process an area of the active layeradjacent the current conduction region (4) to be removed by the etching;and prior to step iii) a second etch mask (36) is formed over the activelayer (10) and the p-n junction current blocking structure (20) adjacentthe current conduction region (4), said second etch mask (36) definingduring an etching process an area of p-n junction current blockingstructure (20) not adjacent the active layer (10) to be removed by theetching.
 10. A method as claimed in claim 8, in which: prior to stepii), an etch mask (126) is formed over the active layer (10), said etchmask defining during a first etching process an area of the active layeradjacent the current conduction region (104) to be removed by theetching; said first etch mask (126) remains during the growth of the p-ncurrent blocking structure (120) in step ii); and said etch mask (126)defines during a second etching process an area of the p-n junctioncurrent blocking structure (20) not adjacent the active layer (10) to beremoved by the etching.